1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device, and more specifically concerns a memory device combining a nonvolatile memory device with a Static Random Access Memory (hereinafter, referred to as “SRAM”).
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a data register of a conventional SRAM. Here, a plurality of data registers are connected to form a SRAM.
The data register comprises a pull-up driving unit 2, a pull-down driving unit 4 and a data input/output unit 6.
The pull-up driving unit 2 comprises PMOS transistors PT1 and PT2 whose gates are cross-coupled with a latch type circuit.
The pull-down driving unit 4 comprises NMOS transistors NT1 and NT2 whose gates are cross-coupled with a latch type circuit.
The data input/output unit 6 comprises switches NT3 and NT4 configured to selectively input and output data with bit lines BL and /BL depending on a voltage applied to a word line WL. Here, the switches NT3 and NT4 are NMOS transistors whose gates are connected to the word line WL.
Hereinafter, the operation of the register of the conventional SRAM is described.
At a write mode, when high level data are loaded on the true bit line BL and a driving voltage Vpp is applied to the word line WL, the switches NT3 and NT4 of the data input/output unit 4 are turned on. Here, the complement bit line /BL is set at a low level.
In the pull-up driving unit 2, the first PMOS transistor PT1 is turned on, and the second PMOS transistor PT2 is turned off.
In the pull-down driving unit 4, the first NMOS transistor NT1 is turned off, and the second NMOS transistor NT2 is turned on.
Here, when the driving voltage Vpp applied to the word line WL is intercepted, the high level data are latched by the pull-up driving unit 2 and the pull-down driving unit 4.
At a read mode, when the driving voltage Vpp is applied to the word line WL, the switches NT3 and NT4 of the data input/output unit 6 are turned on.
For example, when the high level data are stored, the first PMOS transistor PT1 of the pull-up driving unit 2 is turned on, so that the high level data are loaded in the true bit line BL. Here, the second NMOS transistor NT1 of the pull-down driving unit 4 is turned on, so that the complement bit line /BL is set at the low level.
Although the example where the high level data are stored or read is described herein, the low level data are also stored or read by the same operation as described above.
However, the conventional volatile data register loses the stored data when a power is turned off.